1. Field of the Invention
The present invention relates to an apparatus and method for generating an output clock signal having controlled timing, and more particularly to a delay locked loop circuit for ameliorating jitter problems by using a phase blender. A clock-generating apparatus according to the present invention is particularly applicable to semiconductor memory devices and also to all semiconductor apparatuses and computer systems, etc., which require a delay locked loop circuit.
2. Description of the Prior Art
As generally known in the art, the Delay Locked Loop (hereinafter, referring to as xe2x80x9cDLLxe2x80x9d) circuit is a clock-generating apparatus for compensating for a skew between an external clock and data, or between an external clock and an internal clock. FIG. 1 is a block diagram showing an example of a conventional DLL circuit. In the conventional DLL circuit 100, an input buffer 101 receives an external clock signal exCLK or a reference clock signal and converts it into an internal clock signal inCLK or an input clock signal having a signal level adapted to an internal circuit. A variable delay line 103 receives the internal clock inCLK provided from the input buffer 101 and then delays the clock by a predetermined time period, thereby generating an output clock signal dllCLK. A phase detection circuit 105 receives the generated output clock signal dllCLK and the external clock signal exCLK to detect any possible phase difference between the two clock signals. In the case that the phase of an output clock signal dllCLK is ahead of that of an external clock signal exCLK, a phase push signal PUSH is generated. Conversely, in the case that the phase of the output clock signal dllCLK is behind that of the external clock signal, a phase pull signal PULL is generated. Hereinafter, the phase push signal PUSH and phase pull signal PULL are generically referred to as xe2x80x9cphase detection signalxe2x80x9d.
Referring to FIG. 1, a DLL circuit 100 is provided to arrange the output clock signal dllCLK and the external clock signal exCLK. The phase detection circuit 105 detects the phase difference between the output clock signal dllCLK and the external clock signal exCLK to generate the phase pull signal PLL and the phase push signal PUSH. However, inputs to the phase detection circuit 105 are not limited to the above signals, and may also include the internal clock signal inCLK and the output clock signal dllCLK, etc. A line control circuit 107 receives the phase push signal PUSH or the phase pull signal PULL from the phase detection circuit 105, and then generates a control signal CTRL for controlling a delay on a variable delay line 104. Subsequently, the line control circuit 107 provides the signal CTRL to the variable delay line 103.
The DLL circuit 100 shown in FIG. 1 is provided for obtaining the output clock signal dllCLK having the same phase as the external clock signal exCLK mentioned above. This can be achieved by appropriately controlling the delay on the variable delay line 103. The phase detection circuit 105 compares the phase of the external clock signal exCLK with that of the output clock signal dllCLK. If the phase detection circuit 105 determines that the phase of the output clock signal dllCLK is behind that of the external clock signal exCLK, the phase detection circuit 105 activates the phase push signal PUSH. If the phase push signal PUSH is provided to the delay line control circuit 107, the delay line control circuit 107 generates a control signal CTRL responding to the signal PUSH to add a little delay to the variable delay line 103. Through this process, the delay is increased more and more, and as a result, the phase of the output clock signal dllCLK becomes close to the phase of the external clock signal exCLK. Conversely, if the phase detection circuit 105 determines that the phase of the output clock signal dllCLK is behind that of the external clock signal exCLK, the phase detection circuit 105 activates the phase pull signal PULL. This results in decreasing the delay little by little on the variable delay line 103 through the delay line control circuit 107. Through this process, the phase of the output clock signal dllCLK becomes the same as that of the external clock signal exCLK. Under these conditions, the phase of the output clock signal dllCLK is changed by the increased or decreased delay (the delay is a minimum variable delay, and hereinafter, for convenience, referring to as xe2x80x9cunit delayxe2x80x9d) responding to the phase push signal PUSH or the phase pull signal PULL with the center of the phase of the external clock signal exCLK.
The DLL has various performance indexes, and an important one among the indexes is a jitter index. Jitter means a measured value by which the phase of the DLL output signal waves back and forth. The smaller the value gets, the better performance of the DLL gets. An important one among many factors affecting the jitter index is the unit delay on the variable delay line. Accordingly, the jitter index can be improved by decreasing the unit delay.
In order to decrease the unit delay, a method for improving the variable delay line itself has been developed recently. Also, various types of variable delay lines capable of decreasing the unit delay have been developed. However, as things stand now, because the development of the variable line itself has nearly reached its limits of possibility, to further decrease the unit delay has become very difficult.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide an apparatus and method capable of decreasing the next unit delay in a DLL easily without decreasing the unit delay of a variable delay line itself.
Also, another object of the present invention is to provide a delay locked loop circuit for improving the jitter index using a phase blender
In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a circuit for generating an output clock signal having controlled timing, which comprises a first delay circuit which receives an input clock signal in order to generate a first delayed input clock signal, and a second delay circuit which receives an input clock signal in order to generate a second delayed input clock signal.
The first delayed input clock signal is an input clock signal delayed by a period determined according to a first delay control signal inputted to the first delay circuit. The second delayed input clock signal is an input clock signal delayed by a period determined according to a second delayed control signal inputted to the second delay circuit. Also, the clock-generating circuit in accordance with the present invention includes a phase blending circuit for receiving the first and second delayed input clock signals and blending phases of the first and second delayed input signals to generate a phase blended clock signal. The present clock-generating circuit further includes a phase detection circuit and a delay control circuit. After the phase detection circuit receives a reference clock signal and the phase blended clock signal, the phase detection circuit generates a phase push signal in the case that the phase of the phase blended clock signal is ahead of that of the reference clock signal, and generates a phase pull signal in the case that the phase of the phase blended clock signal is behind that of the reference clock signal. The delay control circuit generates a first or second delayed control signal for increasing the delay when receiving the phase push signal from the phase detection circuit and for decreasing the delay when receiving the phase pull signal from the phase detection circuit. The first control signal and the second control signal are generated in alternation. Thus, the first delay control signal and the second delay control signal are not generated simultaneously. In accordance with the present invention described above, it is possible to decrease an effective unit delay easily without decreasing the unit delay of the variable delay line itself, by using one more variable delay line in addition to the present conventional construction and generating a signal having an intermediate phase between the output signals from both variable delay lines.
Preferably, an input buffer is provided to generate an input clock signal by receiving and buffering the reference clock signal. In addition, an output buffer is provided to generate an output clock signal by receiving and buffering the phase blended clock signal. This output clock signal is generated and then supplied to the phase detection circuit, instead of the phase blended clock signal. Also, it is desirable to further provide a dummy delay circuit which receives the output clock signal in order to generate a feedback clock signal. The feedback clock signal is the output clock signal delayed by the delay period generated in the input buffer. In this case, the input clock signal is provided to the phase detection circuit instead of the reference clock signal, and the feedback clock signal is provided to the phase detection circuit, instead of the output clock signal. Also, it is desirable to further provide a dummy delay circuit which receives the output clock signal in order to generate a feedback clock signal. The feedback clock signal is the output clock signal delayed by a predetermined delay period. In this case, the feedback clock signal is provided to the phase detection circuit, instead of the output clock signal.
In accordance with another aspect of the present invention, the above and other objects can be accomplished by the provision of a method for generating a clock signal having controlled timing. Firstly, after an input clock signal and a first delay control signal are received, the input clock signal is delayed by a period determined according to the first delay control signal in order to generate a first delayed input clock signal. Also, after the input clock signal and a second delay control signal are received, the input clock signal is delayed by a period determined according to the second delay control signal in order to generate a second delayed input clock signal. Then, after these first and second delayed input clock signals are received, the first and second delayed input clock signals are blended to generate a phase blended clock signal. Then, after the reference clock signal and the phase blended clock signal are received, in the case that the phase of the phase blended clock signal is ahead of that of the reference clock signal, a phase push signal is generated, and in the case that the phase of the phase blended clock signal is behind that of the reference clock signal, a phase pull signal is generated. Then, a first delay control signal and a second delay control signal are provided to increase the delay when the phase push signal is generated, or on the other hand decrease the delay when the phase pull signal is generated.